Method of manufacturing complementary metal oxide semiconductor device
US8278166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Nov 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.