Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8278764B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2012 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.