Nonvolatile stacked nand memory
US8279656B2 · kind B2 · utility
15Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2010 |
| Grant date | Oct 2, 2012 |
| Priority date | — |
| Expiry date | Apr 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.