One-time programmable memory
US8283731B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.