Dual laminate package structure with embedded elements
US8283767B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.