Delay lines, amplifier systems, transconductance compensating systems and methods of compensating
US8283950B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 2010 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Sep 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.