Handshake free sharing in a computer architecture
US8285895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2007 |
| Grant date | Oct 9, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.