Method of fabricating a recessed channel access transistor device
US8288231B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.