Reduced-stress bump-on-trace (BOT) structures
US8288871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2011 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Apr 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01322
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.