Low power scan testing techniques and apparatus

US8290738B2 · kind B2 · utility

Assignee

• MENTOR GRAPHICS CORPORATION · US

Inventors

• Xijiang Lin · West Linn, US
• Dariusz Czysz · Poznań, PL
• Mark Kassab · Wilsonville, US
• Grzegorz Mrugalski · Ostróda, PL
• Janusz Rajski · West Linn, US
• Jerzy Tyszer · Poznań, PL

Key dates

• Filing date: Mar 16, 2011
• Grant date: Oct 16, 2012
• Expiry date: Mar 16, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318575
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.