Array concatenation in an integrated circuit design
US8291359B2 · kind B2 · utility
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41References
20Claims
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Key dates
| Filing date | May 7, 2010 |
| Grant date | Oct 16, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided in a design environment for array concatenation. The design environment comprises one mechanism to concatenate arrays with enable- and address-compatible ports, thereby reducing the number of arrays in a netlist. The design environment comprises another mechanism to migrate read ports from one array to another based upon compatible enable-, address-, and data-compatible write ports, thereby reducing the number of arrays in a netlist. The design environment comprises yet another mechanism to eliminate unnecessary arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.