Resistive memory and method for controlling operations of the same
US8295075B2 · kind B2 · utility
3Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2010 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Dec 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.