Fault modeling for state retention logic
US8296703B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Nov 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.