Interconnect structure fabricated without dry plasma etch processing
US8298937B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.