Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules
US8299592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Dec 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cube semiconductor package includes one or more stacked together and interconnected semiconductor chip modules. The cube semiconductor package includes a semiconductor chip module and connection members. The semiconductor chip module includes a semiconductor chip which has a first and second surface, side surfaces, bonding pads, through-electrodes and redistribution lines. The second surface faces away from the first surface. The side surfaces connect to the first and second surfaces. The bonding pads are placed on the first surface. The through-electrodes pass through the first and second surfaces. The redistribution lines are placed at least on one of the first and second surfaces and are electrically connected to the through-electrodes and the bonding pads, and have ends flush with the side surfaces. The connection members are placed on the side surfaces and electrically connected with the ends of the redistribution lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.