Area saving electrically-erasable-programmable read-only memory (EEPROM) array
US8300461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.