Error checking parity and syndrome of a block of data with relocated parity bits
US8301988B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.