Select gates for memory
US8304309B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Mar 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.