Method of forming a high-k gate dielectric layer
US8304333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.