Connection between an I/O region and the core region of an integrated circuit
US8304813B2 · kind B2 · utility
0Cited by
14References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2007 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Dec 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.