Method and apparatus of forming a gate
US8304831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jul 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.