Multi-chip stacked package and its mother chip to save interposer
US8304917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip stacked package and its mother chip to save an interposer are revealed. The mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.