Distributed multi-core memory initialization
US8307198B2 · kind B2 · utility
13Cited by
7References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jan 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute the assigned sub-tasks and return the results to the control node, thereby enabling a plurality of processing nodes to efficiently and quickly perform memory initialization and test of all assigned sub-tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.