Minimizing memory array representations for enhanced synthesis and verification
US8307313B2 · kind B2 · utility
3Cited by
41References
20Claims
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Key dates
| Filing date | May 7, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.