Methods for generating code for an architecture encoding an extended register specification
US8312424B2 · kind B2 · utility
2Cited by
25References
11Claims
0Family size
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Key dates
| Filing date | Apr 3, 2008 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Sep 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.