Method for forming a high-K gate stack with reduced effective oxide thickness
US8313994B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/66
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a high-k gate stack with a reduced effective oxide thickness (EOT) for a semiconductor device. The method includes providing a silicon-containing substrate, forming an interface layer on the silicon-containing substrate, where the interface layer has a first equivalent oxide thickness, depositing a first high-k film on the interface layer, and heat-treating the first high-k film and the interface layer at a temperature that forms a modified interface layer, where the modified interface layer has a second equivalent oxide thickness that is equal to or lower than the first equivalent oxide thickness. The method further includes depositing a second high-k film on the modified interface layer. According to one embodiment, the first high-k film includes lanthanum oxide and the second high-k film includes hafnium silicate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.