Patent · US Active

Feature size reduction

US8314034B2 · kind B2 · utility

4Cited by
12References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 23, 2010
Grant dateNov 20, 2012
Priority date—
Expiry dateDec 23, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/0338
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.