Multi-gate bandgap engineered memory
US8315095B2 · kind B2 · utility
30Cited by
140References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2011 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.