Method of manufacture of integrated circuit packaging system with multi-tier conductive interconnects
US8318539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jun 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.