Semiconductor package with stacked chips and method for manufacturing the same
US8319327B2 · kind B2 · utility
6Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Feb 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes at least two semiconductor chips stacked to have step surfaces and possessing bonding pads disposed over the step surfaces. Conductive patterns are disposed over the step surfaces and electrically connect the bonding pads of the semiconductor chips with one another. An insulation member is formed over side and upper surfaces of the stacked semiconductor chips excluding the step surfaces and the conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.