Patent · US Active

SRAM memory cell with double gate transistors provided means to improve the write margin

US8320198B2 · kind B2 · utility

2Cited by

11References

22Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Olivier Thomas · Saint-Martin-d'Hères, FR
Bastien Giraud · Grenoble, FR

Key dates

Filing date	Feb 16, 2009
Grant date	Nov 27, 2012
Priority date	—
Expiry date	Aug 6, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.