Method of fabricating a semiconductor structure
US8324059B2 · kind B2 · utility
96Cited by
75References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 25, 2011 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.