Vias and method of making
US8324103B2 · kind B2 · utility
2Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method of providing a planar substrate with electrical through connections (vias). The method comprises providing a hole in said substrate and a treatment to render the substrate surface exhibiting a lower wettability than the walls inside the hole. The planar substrate is exposed to a molten material with low resistivity, whereby the molten material is drawn into the hole(s). It also relates to a semiconductor wafer as a starting substrate for electronic packaging applications, comprising low resistivity wafer through connections having closely spaced vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.