Method for forming high density patterns
US8324107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Mar 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.