Stacked die module
US8324725B2 · kind B2 · utility
7Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2005 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | May 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.