Patent · US Active

Memory circuit and method for programming in parallel a number of bits within data blocks

US8327062B2 · kind B2 · utility

1Cited by

11References

6Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jan Otterstedt · Unterhaching, DE
Thomas Nirschl · Putzbrunn, DE
Michael Bollu · Munich, DE
Wolf Allers · Munich, DE

Key dates

Filing date	Dec 9, 2008
Grant date	Dec 4, 2012
Priority date	—
Expiry date	Feb 1, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C2013/0088
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first data block and the second data block into the memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. The first and second data blocks may or may not be adjacent data blocks. Improved programming efficiency may be achieved in a memory circuit when the maximum allowable current may be limited by the application or the size of a charge pump. Inverse data may be written in parallel if the sum is greater than the maximum value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.