Techniques for analysis of logic designs with transient logic
US8327302B2 · kind B2 · utility
3Cited by
16References
17Claims
0Family size
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Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Mar 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.