Generating a simulation model of a circuit design
US8327311B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2011 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jul 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.