Strain memorization in strained SOI substrates of semiconductor devices

US8329531B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jan Hoentschel · Dresden, DE
• Sven Beyer · Dresden, DE
• Uwe Griebenow · Markkleeberg, DE
• Thilo Scheiper · Dresden, DE

Key dates

• Filing date: Nov 2, 2010
• Grant date: Dec 11, 2012
• Expiry date: Nov 2, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.