Inventor · Dresden, DE

Thilo Scheiper

72Patents
10h-index
30Co-inventors
70Inventor score

Filing activity: May 28, 2009 → Apr 28, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US8114746B2 Method for forming double gate and tri-gate transistors on a bulk substrate Electricity 35 Active
US8722498B2 Self-aligned fin transistor formed on a bulk substrate by late fin etch Electricity 23 Active
US8936977B2 Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 18 Active
US8703578B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 18 Active
US8975704B2 Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations Electricity 16 Active
US8357604B2 Work function adjustment in high-k gate stacks for devices of different threshold voltage Electricity 14 Active
US7943462B1 Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer Electricity 12 Active
US8409942B2 Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition Electricity 12 Active
US8574981B2 Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same Electricity 12 Active
US8241977B2 Short channel transistor with reduced length variation by using amorphous electrode material during implantation Electricity 10 Active
US8722500B2 Methods for fabricating integrated circuits having gate to active and gate to gate interconnects Electricity 9 Active
US8232188B2 High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning Electricity 7 Active
US8404550B2 Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement Electricity 7 Active
US8524563B2 Semiconductor device with strain-inducing regions and method thereof Electricity 7 Active
US8198152B2 Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials Electricity 7 Active
US8501601B2 Drive current increase in field effect transistors by asymmetric concentration profile of alloy species of a channel semiconductor alloy Electricity 6 Active
US8329531B2 Strain memorization in strained SOI substrates of semiconductor devices Electricity 6 Active
US8679924B2 Self-aligned multiple gate transistor formed on a bulk substrate Electricity 6 Active
US8598007B1 Methods of performing highly tilted halo implantation processes on semiconductor devices Electricity 5 Active
US9184095B2 Contact bars with reduced fringing capacitance in a semiconductor device Electricity 5 Active
US8426266B2 Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices Electricity 5 Active
US9048336B2 Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures Electricity 4 Active
US8669151B2 High-K metal gate electrode structures formed at different process stages of a semiconductor device Electricity 4 Active
US8748281B2 Enhanced confinement of sensitive materials of a high-K metal gate electrode structure Electricity 4 Active
US8916433B2 Superior integrity of high-k metal gate stacks by capping STI regions Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.