Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein
US8329538B2 · kind B2 · utility
15Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.