Patent · US Active

NMOS transistor devices and methods for fabricating same

US8330225B2 · kind B2 · utility

0Cited by

9References

19Claims

0Family size

Assignee

Applied Materials, Inc. · US

Inventors

Sunderraj Thirupapuliyur · San Jose, US
Faran Nouri · Los Altos, US
Yonah Cho · Sunnyvale, US

Key dates

Filing date	Jul 26, 2011
Grant date	Dec 11, 2012
Priority date	—
Expiry date	Jul 26, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.