Nonvolatile memory device having a transistor connected in parallel with a resistance switching device
US8331127B2 · kind B2 · utility
7Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.