Memory array with write feedback
US8331129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.