Patent · US Active

Latch based memory device

US8331163B2 · kind B2 · utility

2Cited by

0References

32Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Siegmar Koeppe · Laatzen, DE
Winfried Kamp · Munich, DE
Julie Aunis · Munich, DE

Key dates

Filing date	Sep 7, 2010
Grant date	Dec 11, 2012
Priority date	—
Expiry date	Sep 21, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/41
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.