Patent · US Active

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

US8334573B2 · kind B2 · utility

0Cited by

1References

16Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Maciej Wiatr · Dresden, DE
Markus Forsberg · Dresden, DE
Stephan Kronholz · Dresden, DE
Roman Boschke · Dresden, DE

Key dates

Filing date	Aug 18, 2010
Grant date	Dec 18, 2012
Priority date	—
Expiry date	Nov 18, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.