Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

US8338284B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Kai Frohberg · Meißen, DE
• Hartmut Ruelke · Dresden, DE
• Volker Jaschke · Radebeul, DE
• Joerg Hohage · Dresden, DE
• Frank Seliger · Dresden, DE

Key dates

• Filing date: Sep 27, 2010
• Grant date: Dec 25, 2012
• Expiry date: Jun 3, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/794
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.