Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices
US8338304B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.