Semiconductor chip with reinforcing through-silicon-vias
US8338961B2 · kind B2 · utility
11Cited by
2References
21Claims
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Key dates
| Filing date | Apr 26, 2012 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Apr 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.