Flip-flop with single clock phase and with reduced dynamic power
US8339172B2 · kind B2 · utility
6Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.